The present invention relates generally to MOS structures incorporated in integrated circuits and in particular the present invention relates to an integrated circuit having a MOS structure with reduced parasitic bipolar transistor action.
Integrated circuits incorporate complex electrical components formed in semiconductor material into a single device. Generally, an integrated circuit comprises a substrate upon which a variety of circuit components are formed wherein each of the circuit components are electrically isolated from each other. Integrated circuits are made of semiconductor material. Semiconductor material is material that has a resistance that lies between that of a conductor and an insulator. Semiconductor material is used to make electrical devices that exploit its resistive properties.
Semiconductor material is typically doped to be either a N type or a P type. N type semiconductor material is doped with a doping type impurity that generally conducts current via electrons. P type semiconductor material is doped with an acceptor-type impurity that conducts current mainly via hole migration. A N type or P type having a high impurity or high dopant concentration or density is denoted by a xe2x80x9c+xe2x80x9d sign. A N type of P type having a low impurity or low dopant concentration or density is denoted by a xe2x80x9cxe2x88x92xe2x80x9d sign.
One type of circuit component is a metal-oxide semiconductor (MOS) transistor. A transistor is a device used to amplify a signal or open and close a circuit. A typical transistor comprises a substrate having layers of varying semiconductor materials that form a source, a drain and a gate. An integrated circuit may comprise a plurality of transistors created from a single substrate to form a circuit.
MOS gated devices, including transistor devices formed in an integrated circuit, typically suffer from degraded performance in safe operating areas and unclamped inductive switching when parasitic bipolar components inherent in MOS gated devices approach their collector-emitter break down voltage (BVCEO). This can be referred to as parasitic bipolar transistor action. Double Diffused Metal Oxide Silicon (DMOS) transistors and Insulated Gate Bipolar Transistors (IGBT), are examples of MOS gated devices. For a NDMOS, the parasitic bipolar component is a NPN.
Referring to the NDMOS example, current can flow from a drain (N type) of the device through a body (P type) positioned under a source (N type) to a surface body contact. The voltage drop developed by this current flow can reach the turn on voltage for the body-source junction along a portion of the junction remote from the surface body contact. That portion of the body-source junction turns on and injects electrons across the body into the drain when the turn on voltage is reached. The blocking voltage of the device drops from proximately BVCBO of the parasitic NPN to approximately collector-emitter break down voltage (BVCEO) of the NPN. This is the basis for reduced performance. The relationship of the breakdown can be approximated by the equation BVCEO=BVCBO/(HFE)xc2xc. Wherein HFE represents a parasitic current gain of a bipolar transistor. HFE can also be referred to as beta. For example, for a parasitic NPN HFE=20, the BVCEO will be about xc2xd the BVCBO. By reducing the HFE, the parasitic bipolar transistor action is reduced thereby enhancing the performance of the device.
The degradation resulting from this parasitic action can be significant. One method of minimizing its impact is to include a P+ body contact region under a portion of the source that is not proximate a channel end of the source where it would cause an unacceptable increase in the threshold voltage. The P+ contact region reduces the resistance through which the current flows thereby increasing the current required to cause the degradation to occur. The use of the P+ contact region provides a useful improvement in device performance but further improvements are desired.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a MOS structure in an integrated circuit that has reduced parasitic HFE levels when the parasitic components are activated.
The above-mentioned problems with high voltage MOS structures and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a metal oxide semiconductor (MOS) integrated circuit device is disclosed comprising a substrate, at least one body region, a layer of narrow band gap material for each body region and a source region formed in each body region. The substrate has a working surface. Each body region is of a first conductivity type. Moreover, each body region is formed in the substrate proximate the working surface of the substrate. Each layer of narrow band gap material is positioned in a portion of its associated body region and proximate the working surface of the substrate. Each layer of narrow band gap material has a band gap that is narrower than the band gap of the substrate in which each of the body regions are formed. Each source region is of a second conductivity type. Moreover, each source region is formed in an associated layer of narrow band gap material.
In another embodiment, a quasi-vertical double diffused metal oxide semiconductor (DMOS) transistor for an integrated circuit is disclosed comprising a substrate, one or more body regions, a source formed in at least one body region and a layer of narrow band gap material. The substrate has a surface. The one or more body regions are formed in the substrate proximate the surface of the substrate. Each of the body regions is of the first conductivity type. Each source is of a second conductivity type with a high doping density. The layer of narrow band gap material is positioned adjacent the surface of the substrate and the body regions. The narrow band gap material has a band gap narrower than a band gap of the body regions. In addition, at least a portion of each source is formed in the layer of narrow band gap material.
In another embodiment, a lateral DMOS transistor for an integrated circuit is disclosed comprising a substrate, a drain contact, a gate, a body, a source and a layer of narrow band gap material. The substrate is of a first conductivity type with a low doping concentration and has a surface. The drain contact is of a second conductivity type with a high doping concentration and is formed in the substrate adjacent the surface of the substrate. The gate is positioned on the surface of the substrate. A body of the first conductivity type is formed in the substrate adjacent the surface of the substrate. A source of the second conductivity type with high doping density is formed in the body. Moreover, the gate is positioned in between the source and the drain contact. The layer of narrow band gap material is positioned in a surface portion of the body and at least a portion of the source. The layer of narrow band gap material has a narrower band gap than the band gap of the substrate.
In another embodiment, a method of forming a MOS device in an integrated circuit is disclosed. The method comprises forming a body region in a substrate adjacent a surface of the substrate. Forming a source in the body region. Forming a layer of narrow band gap material adjacent the surface of the substrate. The layer of narrow band gap material having a band gap narrower than a band gap the substrate material and at least a portion of the source is within the layer of narrow band gap material.
In another embodiment, a method of forming a quasi-vertical NDMOS for an integrated circuit is disclosed. The method comprises forming a patterned first dielectric layer on the surface of the substrate, wherein a first portion of the substrate is exposed by the pattern. Forming a layer of narrow band gap material on the exposed first portion of the surface of the substrate. The layer of narrow band gap material has a band gap that is narrower than the band gap of the substrate. Forming a second dielectric layer on the narrow band gap material. Depositing a gate proximate a medial portion of the second dielectric layer. Forming a pair of body regions in the substrate. The gate is positioned between the body regions. Forming a source in each body region, wherein at least apportion of the source is also formed in the layer of narrow band gap material.
In another embodiment, a method of forming a quasi-vertical NDMOS for an integrated circuit is disclosed. The method comprises forming a patterned first dielectric layer on the surface of the substrate, wherein a first portion of the substrate is exposed by the pattern. Forming a layer of gate dielectric on the exposed first portion of the surface of the substrate. Depositing a gate proximate a medial portion of the layer of gate dielectric. Forming a pair of body regions in the substrate, wherein the gate is positioned between the body regions. Forming layers of narrow band gap material in portions of the body regions. The layers of narrow band gap material have a narrower band gap than the band gap of the remaining portions of the body regions. Forming a source in each body region, wherein at least apportion of the source is also formed in the layer of narrow band gap material.
In another embodiment, a method of forming a lateral DMOS for an integrated circuit is disclosed. The method comprising forming a body of a first conductivity type in a substrate of a first conductivity type with a low doping density, wherein the body is positioned adjacent a surface of the substrate. Forming a layer of narrow band gap material in each body region adjacent the surface of the substrate. The layer of narrow band gap material has a band gap that is narrower than the band gap of the remaining portions of the body region. Forming a source of a second conductivity type with a high doping density in the body, wherein at least a portion of the source is formed in the layer of narrow band gap material. The narrow band gap material suppresses carrier injection form the source into the body thereby reducing parasitic HFE.
In another embodiment, a vertical DMOS device is disclosed comprising a substrate, at least one gate, a dielectric layer insulating each gate from the substrate, a drain region formed in the substrate, at least one body region, a layer of narrow band gap material and a source for each body region. The at least one body region is formed in the substrate adjacent the drain region and proximate a working surface of the substrate. The layer of narrow band gap material is formed in each body region adjacent the surface of the substrate. The layer of narrow band gap material has a narrower band gap than the band gap of the remaining portions of the body region. Each source is formed in an associated body region. At least a portion of each source is also formed in the layer of narrow band gap material. The layer of narrow band gap material suppresses carrier injections from each of the source regions into associated body regions thereby reducing HFE.
In another embodiment, a method of forming a vertical DMOS is disclosed. The method comprises forming a drain region in a substrate of a first conductivity type with a low dopant density. Forming a body region in the substrate of a second conductivity type over the drain region. Forming a layer of narrow band gap material in the substrate, wherein the layer of narrow band gap material has a narrower band gap than portions of the body region. Forming at least one source region of the first conductivity type with high dopant density in the body, wherein at least a portion of each source region is formed in the layer of narrow band gap material. Forming at least one gate.
In another embodiment, a switching power supply control circuit is disclosed comprising a diode bridge, a transformer, a quasi-vertical DMOS transistor and control circuitry. The diode bridge is used to perform full rectification of the input AC voltage. The transformer is coupled to the diode bridge to provide galvanic isolation and voltage conversion. The quasi-vertical DMOS transistor coupled to control the voltage through the transformer. The control circuitry is coupled to a gate of the quasi-vertical DMOS transistor to switch the DMOS transistor on and off, wherein the control circuitry controls a duty cycle of the DMOS transistor to achieve a desired output from the transformer. The quasi-vertical DMOS transistor comprises a substrate, one or more body regions, a source for each body region and a layer of narrow band gap material. The substrate is of a first conductivity type with a low doping density. The substrate has a surface. The gate is formed overlaying the surface of the substrate. The one or more body regions are formed in the substrate proximate the surface of the substrate. Each of the body regions is of the first conductivity type. Each source is of a second conductivity type with a high doping density. Each source and each body are positioned proximate an associated edge of the gate. The layer of narrow band gap material is positioned adjacent the surface of the substrate and the body regions. The narrow band gap material has a band gap narrower than the semiconductor material of the body. In addition, at least a portion of each source is formed in the layer of narrow band gap material to reduce parasitic bipolar transistor action.
In yet another embodiment, a solid state relay integrated circuit is disclosed comprising a photo diode stack, a first high voltage lateral DMOS and a second high voltage lateral DMOS. The photo diode stack is used to drive a voltage having a first output and a second output. The first high voltage lateral DMOS has a gate, source and drain. The gate of the first high voltage DMOS is coupled to the first output of the photo diode stack. The source of the first high voltage DMOS is coupled to the second output of the photo stack diode. The second high voltage lateral DMOS has a gate, source and drain. The gate of the second high voltage lateral DMOS is coupled to the first output of the photo diode stack. The source of the second high voltage lateral DMOS is coupled to the second output of the photo diode stack. The first and second high voltage lateral DMOS comprise a substrate, a drain contact, a gate, a body, a source, and a layer of narrow band gap material. The substrate is of a first conductivity type with a low doping concentration. The substrate has a surface. The drain contact is of a second conductivity type with a high doping density. The drain contact is formed in the substrate adjacent the surface of the substrate. The gate is positioned on the surface of the substrate. The body is of the first conductivity type and is formed in the substrate adjacent the surface of the substrate. The source is of the second conductivity type with high doping concentration and is formed in the body adjacent a surface of the substrate. The gate is positioned in between the source and the drain contact. The layer of narrow band gap material is positioned on the surface of the substrate adjacent the body and at least a portion of the source to reduce parasitic bipolar transistor action. In addition, the layer of narrow band gap material has a narrower band gap than the band gap of the substrate.